My background is in computer science. I studied my bachelor and master degree at National Taiwan University. During my bachelor degree, I've been studied basic CS knowledge, such as data structure, algorithm and operating system. To explore different views, I also touched multimedia and machine learning areas. After that, to have a solid system background, during my master degree, I focused on computer system and architecture, working with Prof. Chia-Lin Yang on topics related to nonvolatile memories. Before my master graduation, I also collaborated with Prof. Jishen Zhao. Now, I am interested in operating/embedded system and network backend.

• GPA: 4.15/4.3
• Master's Thesis: Nonvolatile Transaction Cache for Efficient Persistence Guarantee
  • Full system evaluation on MARSSx86+DRAMSim2 simulator (C/C++, Perl, Python)

• GPA: 3.99/4.3
• Awards: Presidential Award (Top 5%) in 2nd Semester 2010/2011 and 1st Semester 2013/2014

• A C-- compiler implemented with following features:
  • Implicit type conversions, Assignment statements, Arithmetic expressions, Control statements (while, if-then-else, for), Procedure calls, Read and Write I/O calls, Short-circuit boolean expressions, Variable initializations, Multiple dimensional arrays.

• Implementation of Shadow Stack on qemu-0.13 to improve indirect brach handling routines
• Analyzation of multiple virtual machines (Qemu) behaviors on KVM
• LMbench is applied to analyze the memory interferences between VMs.

• Experimental Platform:
  • Simulator: USIMM: the Utah SImulated Memory Module and its modified PARSEC traces
• An enhanced DRAM scheduling policy is proposed.
  • Row Hit Aware: Serve row hit request first and apply close page when no remaining row hit requests.
  • No Idle Read/Write mode: Issue write/read at idle time during read/write mode due to dependencies.
  • Thread Aware: Serve compute-intensive requests first to make CPU fully utilized and reduce memory interferences.

• Experimental Platform:
  • Hardware: AMD Kaveri APU (A10-7850K), Heterogeneous Unified Memory Architecture (hUMA)
  • Operating System: Ubuntu 14.04 LTS | Driver: AMD Catalyst Driver
• Analyzation of different behaviors on CPU and GPU of benchmarks from parboil and rodinia suits
• A two-stage scheduling method is proposed to reduce memory interferences and balance execution time of CPU and GPU.

• Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach
  Chun-Hao Lai, Jishen Zhao, and Chia-Lin Yang
  In Proceedings of the 54th Annual Design Automation Conference 2017 (DAC '17)
  
• Fine-Grained Write Scheduling for PCM Performance Improvement under Write Power Budget
  Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang and Hsiang-Pang Li
  In Proceedings of the 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED '15)
  

Programming Languages: Proficient: C/C++ ‧ Familiar: Java ‧ Basic: HTML/CSS, JavaScript, Perl, Python